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DS2740
READ-TIME SLOTS 
A read-time slot is initiated when the bus master pulls the 1-Wire bus line from a logic-high level to a
logic-low level. The bus master must keep the bus line low for at least 1?/SPAN>s and then release it to allow the
DS2740 to present valid data. The bus master can then sample the data t
RDV
 from the start of the read-
time slot. By the end of the read-time slot, the DS2740 releases the bus line and allows it to be pulled
high by the external pullup resistor. All read-time slots must be t
SLOT
 in duration with a 1?/SPAN>s minimum
recovery time, t
REC
, between cycles. See Figure 12 for more information.
 
Figure 12. 1-Wire WRITE- AND READ-TIME SLOTS  
 
 
 
 
 
 
14 of 16
 
 
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